In U.S. Pat. No. 6,479,351 to Lojek et al., incorporated by reference herein, there is disclosed a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed from conductive polysilicon on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate and is thicker between the main floating gate region and the substrate. The thin oxide region is thin enough to be an electron tunneling medium, i.e. a pathway for electrons to tunnel into the floating gate from a substrate electrode. The thin oxide layer is brought up vertically along a wall of the main floating gate region, separating the main floating gate region from the spacer, allowing charge entering the thin oxide to migrate out in opposite directions, i.e. into the main floating gate body or into the sidewall spacer. Both the main floating gate body and the sidewall spacer are made of polysilicon and are electrically connected so that both have the same electrical potential. A control gate overlying the main floating gate body and the sidewall spacer can draw charge from the substrate into these structures by application of a programming voltage where the charge will remain until an opposite programming voltage causes discharge of the structures.
Japanese Patent Publication No. 11154712 by K. Kenichi of NEC Corp. shows a similar structure.
While the spacer floating gate memory cells disclosed in the '351 patent are very useful, an object of the invention was to devise a way to make spacer floating gate memory cells more compact for use in large scale memory arrays.